Course Outline

The origins of the RISC-V architecture are explored, including its modular design principles that encompass base architectures and various extensions. The RISC-V Instruction Set Architecture (ISA) is detailed, covering registers and the instruction set, as well as features aligned with contemporary software concepts. An overview of RISC-V implementations for government applications is also provided.

The system architecture of RISC-V is examined, focusing on exception handling mechanisms. The CLIC interrupt controller is introduced, along with a specific look at the ECLIC interrupt controller in the GD32VF103 processor, which is relevant to public sector workflows and governance.

Exercises:
1. Firmware development for the GD32VF103 using VScode.
2. Interrupt handling on the GD32VF103.

Requirements

Fundamental understanding of the C programming language is required for government professionals.

 7 Hours

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