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Course Outline
RISC-V Architecture Fundamentals and Ecosystem Overview
RISC-V Instruction Set Architecture Landscape and Sector Adoption
- Open instruction set philosophy and the RISC-V International standardization framework
- Conceptual model of RISC-V: Load-Store architecture, register file organization, and byte ordering conventions
- Comparative analysis with ARM, x86, and POWER architectures: evaluating trade-offs for heterogeneous computing systems
- Ecosystem maturity assessment: contributions from SiFive, T-Head, Western Digital, and the expanding open-source silicon community
- Standardized interfaces: RISC-V Privileged ISA and the Machine Software Abstraction Layer (MSBL)
Memory Models and ABI Compliance
- Unprivileged Architecture specifications: Control and Status Register (CSR) mapping, exception handling protocols, and memory hierarchy structures
- RV32I and RV64I instruction set definitions and ABI compliance ensuring cross-platform binary portability
- Memory ordering conventions and barrier instruction implementation for multiprocessor environments
RISC-V Assembly Programming and Compiler Toolchain
Low-Level Instruction Programming
- Base integer instructions (I), Multiply/Divide (M), and Atomic operation (A) extension implementations
- Bitness-aware programming strategies for 32-bit and 66-bit RISC-V target systems
- Calling conventions and stack frame management tailored for embedded and real-time software applications
Compiler Toolchain Proficiency
- LLVM-based compiler infrastructure: Clang, LLVM, and Binutils utilization for RISC-V cross-compilation
- Linker script configuration, section definition, and memory layout optimization for bare-metal and RTOS environments
- Compiler intrinsic usage, optimization level adjustments, and profiling-driven performance tuning
- Open-source toolchain development workflows: building, testing, and packaging custom GCC/Clang toolchains
Embedded Systems Development and Real-Time Operating Systems
Bare-Metal and RTOS Programming
- Rust systems programming for RISC-V: zero-cost abstractions, unsafe memory management, and bare-metal development practices
- No-Std environment configuration: custom linker implementation, device driver development, and memory-mapped I/O handling
- Zephyr RTOS and Buildroot BSP development specifically for RISC-V target architectures
- Peripheral interfacing protocols: GPIO, I2C, SPI, UART, and DMA controller programming standards
Power and Performance Optimization
- Clock gating techniques, power domain management, and low-power mode optimization strategies
- Cycle-accurate performance analysis utilizing simulation profilers and hardware performance counters
- Real-time interrupt latency optimization for safety-critical operational applications
Linux Kernel and Bootloader Development for RISC-V
Boot Firmware and Bootloader Ecosystem
- OpenSBI implementation (SBI specification): bootloader firmware development for RISC-V platforms
- UEFI/EDK II implementation on RISC-V: modern firmware boot stack architecture and development
- Coreboot and U-Boot porting processes for RISC-V single-board computer hardware
Linux Kernel Integration
- RISC-V mainline kernel contributions: device tree overlay management, CPU topology configuration, and Advanced Interrupt Architecture (AIA) driver development
- Vendor BSP development and kernel configuration tuning for custom System-on-Chip (SoC) platforms
- File system support, networking stack integration, and containerization support (Docker, Kubernetes) on RISC-V host systems
RISC-V SoC Design and FPGA Prototyping
Multicore SoC Architecture and Integration
- Network-on-Chip (NoC) design methodologies for RISC-V multi-core processor systems
- Axi4/CHI cache coherence protocols and inter-processor communication mechanisms
- Open-source IP integration: OpenCores, ChIPS Framework, and vendor-specific RTL components
- Bus matrix design and memory controller integration for DDR, SRAM, eMMC, and PCIe interfaces
FPGA-Based Processor Prototyping
- FPGA synthesis and implementation of RISC-V cores (e.g., BOOM, VexRiscv, PULP)
- SystemVerilog Assertions (SVA) and UVM-based functional verification methodologies
- Formal verification tools and property-based testing frameworks for RISC-V core validation
RISC-V Vector Extensions and Domain-Specific Acceleration
RVV (RISC-V Vector) Extension Deep Dive
- Vector load/store operations, vector fused multiply-add (VFMA), and matrix computation acceleration techniques
- Variable-length vector operations (VL, VLEN) implementation for workload-optimized SIMD execution
- Vector mask operations, segment control logic, and data type flexibility for DSP and machine learning workloads
Custom DSP and Domain-Specific Instruction Design
- Domain-specific accelerator design through custom extensions and CBAR-based operand interfaces
- Compiler frontend modifications to support custom instruction generation and code emission
- Hardware-software partitioning strategies for integrating accelerators in production SoC designs
AI Acceleration and Edge Machine Learning on RISC-V
NPU Design and Integration for RISC-V Processors
- Neural Processing Unit architecture: systolic arrays, tensor cores, and weight compression for on-chip AI acceleration
- Model quantization techniques (INT8, INT4, FP8) for efficient edge deployment on RISC-V hardware
- Framework compatibility: TensorFlow Lite Micro, ONNX Runtime, and PyTorch Edge implementation on RISC-V targets
Heterogeneous Computing for AI Workloads
- Co-design of RISC-V host CPU with AI accelerator NPU for real-time inference pipeline management
- Memory subsystem optimization: HBM/DDR bandwidth management for ML model weights and activation data
- Thermal and power budgeting considerations for edge AI inference systems
Hardware Security and Confidential Computing on RISC-V
Physical Memory Protection and Trusted Execution
- Physical Memory Protection (PMP) mechanisms and Page Table walker security implementations
- Secure Enclave/TEE architectures for RISC-V: OP-TEE integration and SEV-class trusted execution environments
- Boot chain security: establishing root of trust, secure boot processes, and measured launch attestation
Cryptographic Acceleration
- RISC-V cryptographic extensions (Zk, Zkr, K extensions): SHA, AES, RSA, RSA-PSS, and ECC acceleration capabilities
- Post-quantum cryptography (PQC) integration for next-generation RISC-V processor designs
- Side-channel attack mitigation techniques: constant-time programming, masking, and hardware random number generator utilization
Advanced Custom Architecture and ISA Extension Design
Domain-Specific Architecture and Custom Instruction Extensions
- ISA extension design methodology: encoding schemes, encoding tables, ABI impact analysis, and RISC-V International specification submission protocols
- Custom register file design with CBAR (Custom Base Address Registers) for operand dispatch optimization
- Instruction pipelining, hazard detection, and pipeline modifications to support custom extensions
Verification and Signoff of Custom Architecture Modifications
- Testbench design for custom extensions: directed vs. constraint-random stimulus generation strategies
- Regression testing frameworks and coverage-driven verification for architectural modifications
- Interoperability testing: ensuring custom instructions function within established ABI constraints
Safety-Critical and Automotive RISC-V Applications
Functional Safety and Automotive Standards Compliance
- ISO 26262 functional safety compliance strategies for RISC-V automotive processors
- ASIL-Q classification and safety manual development for RISC-V silicon IP components
- Deterministic interrupt handling, lockstep core pairs, and memory protection mechanisms for safety-critical RISC-V systems
Industrial Real-Time and Edge Computing Applications
- IEC 61508 SIL compliance and deterministic scheduling on RISC-V multicore platforms
- Industrial IoT gateway development with RISC-V: connectivity standards, edge analytics, and OTA firmware update systems
Capstone Project: End-to-End RISC-V System Development
Full Lifecycle Project
- Architecture specification: ISA extensions and core configuration design for a defined operational use case
- RTL implementation in SystemVerilog with UVM testbenches and formal verification coverage
- FPGA prototyping, boot firmware development, and bare-metal driver stack integration
- Linux BSP and toolchain customization for the custom RISC-V core
- AI workload deployment: NPU integration, model quantization, and performance benchmarking
- Security validation: PMP enforcement, secure boot verification, and cryptographic acceleration benchmarking
- Technical architecture documentation, IP strategy analysis, and cross-functional team presentation
Requirements
None.
21 Hours
Testimonials (2)
The explanations and interactivity of the trainer, he really brought the subject well; and even-though I was probably not experienced enough, I did learn a lot from it!
Pieter Bruynseels - Spot Buy Center BV
Course - Design Patterns
That we could you real life examples
